﻿===========================================================================================
QUANTA Computer Inc. BIOS RELEASE NOTES for S5B/S5BM/S5BQ/S5BT/S5BV/S5D/S5S/S5SP/S5T/S5BE
===========================================================================================
Project Name      : S5B/S5BM/S5BQ/S5BT/S5BV/S5D/S5S/S5SP/S5T/S5BE
BIOS Version      : 3B27.Q401
Build Date        : 2023/07/12
Update BootBlock  : YES
Clear NVRAM       : YES
BIN Checksum(32MB): 5963531F
ROM Checksum(16MB): A450568F
BIN_enc Checksum  : 596392B4
BIN MD5(32MB)     : E5C1C37E0BE362BE69EE02D6C1F2D023
ROM MD5(16MB)     : FA0377A7E7C409E93BD693FFFF1EA2DA
BIN_enc MD5       : A0F9649FF4051D6E888DF9E2C0B4ACA9

===========================================================================================
                             HARDWARE REQUIREMENTS/REVISIONS
===========================================================================================
System hardware revision supported: S5B/S5BM/S5BQ/S5BT/S5BV/S5D/S5S/S5SP/S5T/S5BE motherboard. (B0/B1/S0/S1 PCH)

===========================================================================================
                             INTEL PROCESSOR MICROCODE REVISIONS
===========================================================================================
----------------------+----------------------------------------------------+---------------
Filename              | Description                                        | Stepping(s)     
----------------------+----------------------------------------------------+---------------
MB750654_02007006.mcb | H-0/M-0/U-0 stepping processor signature 00050654  | H-0/M-0/U-0 (Skylake Server)
MB750655_03000012.mcb | A-0         stepping processor signature 00050655  | A-0 (CascadeLake Server)
MBf50656_04003604.mcb  | B-0/L-0/R-0 stepping processor signature 00050656  | B-0/L-0/R-0 (CascadeLake Server)
MBf50657_05003604.mcb  | B-1/L-1/R-1 stepping processor signature 00050657  | B-1/L-1/R-1 (CascadeLake Server)
----------------------+----------------------------------------------------+---------------

===========================================================================================
                             SYSTEM FIRMWARE REQUIREMENTS/REVISIONS
===========================================================================================
BIOS Core Version                 : 5.14
BIOS Compliancy                   : UEFI 2.7.0; PI 1.6
AMI BIOS Label                    : 5.14_PurleyCrb_0ACLA060
VGA (embedded in AST2500)         : 1.08.00
Intel(R) SPS F/W (ME)             : SPS_E5_04.01.05.002.0 
PTT version                       : 302.8
BMC Override XML Version          : v15 (Override)
Intel(R) RC                       : 0628.P50
Intel(R) BIOS ACM                 : v1.7.54 (PW)
Intel(R) SINIT ACM                : v1.7.55 (PW)
Intel(R) RSTe PreOS Components    : v8.0.0.4006 
HFI1 UEFI Driver                  : v1.9.2.0
FPK X722 GbE FW                   : LBG_B1_PHY_Auto_Detect_NCSI_LED_ACT_QCTv004_v3.45_80000B4B.bin
Lewisburg X722 GbE UEFI driver    : 2.5.07
Lewisburg X722 GbE PXE OPROM      : 1.0.66
Lewisburg X722 GbE iSCSI OPROM    : 3.1.29
EEPROM version of NVM image       : 0004
AFU version                       : v5.15.04.0098
Intel BKC Version                 : KIT #777696
QS DCPMM Module Firmware          : fw_ekvb0_1.2.0.5446_rel.bin

===========================================================================================
                             IMPORTANT INSTALLATION NOTES
===========================================================================================
WARNING:
A. It is very important to follow the flash option provided in the batch file (BIOS_efi64.nsh/
   ME_efi64.nsh for UEFI Shell, BIOS_win64.cmd/ME_win64.cmd for Windows 64 bits, BIOS_lnx64.sh/ME_lnx64.sh for Linux 64 bits). 
   Using incorrect flash option to flash BIOS may cause damage to your system.

B. After BIOS 3B02, system will not support DCPMM(or AEP) DIMM firmware 01.00.00.4707(BKC WW17) or earlier version.
   Please update your DCPMM firmware to BKC WW20 or later before flashing BIOS 3B02 or later.

C. Please update the DCPMM FW to corresponding version prior to the update of the BIOS.

1. Burn 3Bxx.BIN via fixture

2. For UEFI  Shell environment, follow below steps to update BIOS:
   (1) Unzip the release package to the same folder in a HDD or USB Flash Drive.
   (2) Insert the USB Flash Drive or HDD mentioned in step (1).
   (3) Power on the system and boot into "Build-in EFI Shell"
   (4) Execute batch file BIOS_efi64.nsh to update BIOS.
   (5) Execute batch file ME_efi64.nsh to update ME FW.
   (6) After the update finished, reboot the system, the new BIOS/ME FW runs.
   (7) Enter BIOS setup, press <F9> to load default and save before any test run.
 
3. For x64 Windows environment, follow below steps to update BIOS:
   (1) Power on the system and boot into Windows OS.
   (2) Unzip the release package to the same folder in the HDD.
   (3) Open Command Prompt, change to the folder with release package located.
   (4) Execute batch file BIOS_win64.cmd to update BIOS.
   (5) Execute batch file ME_win64.cmd to update ME FW.
   (6) After the update finished, reboot the system, the new BIOS/ME FW runs.
   (7) Enter BIOS setup, press <F9> to load default and save before any test run.
   
4. For x64 Linux environment, follow below steps to update BIOS:
   (1) Power on the system and boot into Linux OS.
   (2) Unzip the release package to the same folder in the HDD.
   (3) Open Terminal, change to the folder with release package located.
   (4) Type "chmod -R 777 *" to change privilege for all files and folders.
   (5) Execute batch file BIOS_lnx64.sh to update BIOS.
   (6) Execute batch file ME_lnx64.sh to update ME FW.
   (7) After the update finished, reboot the system, the new BIOS/ME FW runs.
   (8) Enter BIOS setup, press <F9> to load default and save before any test run.
   
5. If update BIOS from version before 3Axx(include 3Axx) to 3Bxx, please use WebUI or fixture to update.
   
Note:
- Before BMC 3.62, it may have 'PHY MAC restore to default'/'PHY become busy under OS' by inband/outband YAFUFLASH flash BIOS.
- After BMC 4.22, please use BIOS *.BIN_enc file to update BIOS by BMC outband support.
- BIOS_efi64.nsh/BIOS_win64.cmd/BIOS_lnx64.sh updates BIOS region only.
- ME_efi64.nsh/ME_win64.cmd/ME_lnx64.sh updates non-BIOS regions (include 10GbE/ME/PDR ...).
- AFUDOS tool is no longer supported, we provide UEFI/Windows/Linux environment tool for upgrade firmware.
- This BIOS already enable Security Flash feature, please make sure the BIOS image signed when you want upgrade it.
  Or it will report security check fail then upgrade fail.
- After 3A01, BIOS will into PVT phase, some option default value will change by followed SI Standard Spec, please notice this.
- Please make sure the PHY ID match with the current system run NVM image, or X722 device will only left one and can't work.
- BIOS has support PLDM function to keep the setting after flashing BIOS, please confirm updated parameters include "/N /CLRCFG",
  if need to back to the default setting.
  ex. In x64 Linux environment, after BIOS_lnx64.sh execution for BIOS udpated, "./afulnx64\Afulnx_64 3Bxx.BIN /N /CLRCFG" to load default.
      In UEFI Shell environment, after BIOS_efi64.nsh execution for BIOS udpated, "afuefi64\AfuEfi64.efi 3Bxx.BIN /N /CLRCFG" to load default.
      In x64 Windows environment, after BIOS_win64.cmd execution for BIOS udpated, "afuwin64\afuwinx64.exe 3Bxx.BIN /N /CLRCFG" to load default.
- The Lewisburg X722 controller use 40 GbE driver, the ctrl+S function was removed after UEFI driver 1.6.20 version.
- BIOS will not support to update Lewisburg X722 NVM image in AFU updating process.
  Please use "NVM update tool" to update this image manually in OS.
- Project S5B series/S5S series/S5D/S5T has multi-default setting, so POST error "CMOS/NVRAM configuration cleared" 
  will not present in POST screen, but it will be logged into SEL.
- Configuration rules related with DCPMM "must be followed":
  1. DCPMMs of capacities, firmware and stepping must be the same.
  2. DCPMMs of firmware need matching BKC version.
  3. DCPMMs of population recommend to follow INTEL's suggest.
  4. DCPMMs controller stepping must be same. If no follow, it will result in UEFI Fatal Error “DIMM controller revision mismatch”.
  5. Each DCPMM in the system must have the same SKU(ES or QS) with respect to the operating modes and features supported.
     If the DCPMM software detects that the system is populated with DCPMM with incompatible SKUs, it will operate in read-only mode.
     In this case, it will not allow changes to the DCPMMs and their associated capacity.
- Starting from 2018_WW46 BKC, Intel do NOT validate on RHEL 7.5.
- From BIOS 3B09, BIOS use the Production Worth(PW) ACM Binary and "must" use production CPU samples.
  If TXT feature with PW ACM used on a platform with engineering samples, system may reset.
- According to Intel datasheet #556488 – Intel® Optane™ DC Persistent Memory Module Firmware Interface Specification, Revision 1.13,
  if Revision Number(RN) of DCPMM firmware is updated, DCPMM cannot be downgraded to a FW version whose RN is less than present version.
  Firmware version    01.02.00.5318
                       |  |  |    +--- 4-digit Build Number
                       |  |  +-------- 2-digit Security Revision Number (SV)
                       |  +----------- 2-digit Revision Number (RN)
                       +-------------- 2-digit Product Number (PN)
- After BKC 2018_WW50, ES2 firmware is no longer updating.

- Starting from 2019_WW08 BKC, BIOS enabled Short ARS on boot. Please wait for ARS to complete before updating the DCPMM FW.
- Do not downgrade DCPMM DIMMs to a version of DCPMM FW below PV/PRQ FW 1.2.0.5355 (2019_WW08 BKC).
  Older DCPMM FW will not be supported and DIMMs could enter an undesired state effecting usability.
- For enabling Intel SST-BF, Linux kernel must be updated to 5.2 or later version.
- After "Flash Descriptor Region Lock" solution updated, there are 3 conditions need user to reflash BIOS by OOB one time
  for BIOS to configure correct settings.(conditions - PCIe riser change/both PHY board remove or add cases/ Board ID update)
  Must actions(follow the sequences) for BIOS to configure correct settings: 
  1. New PCIe riser install.
  2. Both PHY board remove or add on MB.
  3. Flash Board ID.
  4. OOB flash BIOS.
  5. DC cycle, new setting will take effect.
- The Linux script 'ubios_oob.sh' is designed for factory production,it is not for end user.
- Since 3B21.Q402 starts to lock the "Descriptor Region", 
  and the code changes to disable CPU/BIOS Write/Read Device Expansion Region are included in "Descriptor Region", 
  so if you use a BIOS version later than 3B21.Q402, you need to OOB flash to the 3B24.Q101 BIOS then the changes can take effect.

===========================================================================================
                             KNOWN ISSUES/WORKAROUNDS
===========================================================================================  
- According to Intel security advisory, BIOS is default disabled DCI interface by SPS ME xml and BIOS setup.
  This is a notice from Intel eMOW WW08, and TXT only works when DCI disable and no ITP connected.
  Also, DCI related setup has been removed since BIOS 3B02 per security concern.
  
- Because RSD feature already implemented, it will send whole SMBIOS table with all system information to BMC. At the first new configuration 
  environment, BIOS will take a lot of time to send data while boot into OS or Shell.
  
- Please notice that if you execute BIOS online upgrade script continuous twice (after flash completely then execute again).
  The PLDM module will override the BIOS default again. It's current PLDM limitation, please do not execute BIOS upgrade script continuous.

- BIOS would skip flashing Lewisburg X722 GbE region in AFU ME update, please use addiotnal Intel nvmupdate tool to update 
  Lewisburg X722 GbE region when flash BIOS by AFU tool. But using WebUI can update BIOS version and Lewisburg X722 GbE region at the same time.

- The device strings of each boot option in Setup pop-up screen are limited to one line temporarily.
  Therefore some long device strings may be cut out in the end.
  
- AFU BIOS flashing between version 3B01 and 3B02 cannot enable PLDM feature, i.e. cannot preserve BIOS Setup modifications after updating BIOS image.

- "The ROM file information does not match with the system BIOS!" warning messages will appear when using 
  AFU tool to flash BIOS with rom layout change.
  Please add "/RLC:E" parameter in AFU scripts to flash BIOS image, or press "E" if ROM layout change warning messages appear.

- BIOS cannot detect MAC address in legacy boot mode on Mellanox LAN card ConnectX-4, ConnectX-5 in IB mode.

- Cascade Lake Server Qual (Intel® Xeon® Processor Scalable Family A0) has several issues that either limit or prevent 
  some capabilities of DCPMM from being evaluated. The Intel® Optane™ DC Persistent Memory Technology Sightings Report, 
  Doc #569957, contains details on features and functionality that are known to be blocked or affected by UEFI FW, 
  DCPMM Firmware, and other parts of the software stack.

- Apache Pass in Appdirect Mode when used with Windows RS5 may go into an non-reconfigurable state. Under investigation EIP-433841 IPS-00387013.

- If user uses WebUI outband "BIOS Update" to flash BIOS image and selects "Preserve BIOS NVRAM Region" during BIOS update process, 
  Setup option "Correctable Error Threshold" value may not be modified according to BIOS default.
  Please do not select "Preserve BIOS NVRAM Region" during WebUI outband "BIOS Update" process, if "Correctable Error Threshold" value update is required.

===========================================================================================
                             FEATURES ADDED/MODIFY
===========================================================================================
3B27.Q401:
- Follow 5.14_PurleyCrb_0ACLA060 to update related modules RC0628.P50 (2023.3 IPU PV)
- Update SKX CPU H0 stepping microcode to MB750654_02007006.
- Update CLX CPU B0 stepping microcode to MBF50656_04003604.
- Update CLX CPU B1 stepping microcode to MBF50657_05003604.
- Update Intel(R) SPS F/W to SPS_E5_04_01_05_002_0.
- implement WA for sSATA device boot option would disappear after change AHCI mode to RAID mode

3B26.Q301:
- Follow 5.14_PurleyCrb_0ACLA059 to update related modules RC0627.P11 (2023.2 IPU PV)
- Update SKX CPU H0 stepping microcode to MB750654_02006f05.
- Update CLX CPU B0 stepping microcode to MBF50656_04003501.
- Update CLX CPU B1 stepping microcode to MBF50657_05003501.

3B25.Q201:
- Follow 5.14_PurleyCrb_0ACLA058 to update related modules RC0626.P01 (2023.1 IPU PV)
- Update CLX CPU B0 stepping microcode to MBF50656_04003303.
- Update CLX CPU B1 stepping microcode to MBF50657_05003303.
- Update Intel(R) SPS F/W to SPS_E5_04_01_04_901_0.
- Setup modify: Hide "CAT Opportunistic Tuning" option

3B24.Q101:
- Follow 5.14_PurleyCrb_0ACLA057 to update related modules RC0623.D09 (2022.3 IPU PV)
- Update SKX CPU H0 stepping microcode to MB750654_02006E05.
- Update Intel(R) SPS F/W to SPS_E5_04_01_04_804_0.
- Follow latest Intel SPI program guide spec "intel-c620-pch-spi-program-guide-559021-rev1-3.pdf" 
  Table 4-1 to disable CPU/BIOS Write/Read Device Expansion Region.

3B23.Q301:
- Follow 5.14_PurleyCrb_0ACLA055 to update related modules RC0618.D03 (2022.1 IPU PV)
- Update SKX CPU H0 stepping microcode to MB750654_02006d05.
- Update CLX CPU B0 stepping microcode to MBF50656_04003302.
- Update CLX CPU B1 stepping microcode to MBF50657_05003302.
- Update Intel(R) SPS F/W to SPS_E5_04_01_04_700_0.

3B22.Q201:
- Follow 5.14_PurleyCrb_0ACLA054.01 to update related modules RC0616.D08 (2021.2 IPU PV)
- Update SKX CPU H0 stepping microcode to MB750654_02006c0a.
- Update CLX CPU B0 stepping microcode to MBF50656_0400320a.
- Update CLX CPU B1 stepping microcode to MBF50657_0500320a.
- Update Intel(R) SPS F/W to SPS_E5_04_01_04_601_0.
- Follow Purley snapshot to update SMBIOS type 4 Max Speed for Skylake

3B21.Q402:
- Update DBX binary that UEFI web posted on April 29, 2021.

3B21.Q401:
- Follow 5.14_PurleyCrb_0ACLA053 to update related modules RC0612.D02 (2021.1 IPU PV)
- Update CLX CPU B0 stepping microcode to MBF50656_04003103
- Update CLX CPU B1 stepping microcode to MBF50657_05003103
- Modify option "tRFC Performance Enable" default to [Enable] for better result of performance testing.
- Update SMBIOS type 4 Max Speed for Skylake.
- Modify Security Vulnerability (CVE-2021-28211 / CVE-2021-28210 / CVE-2019-14584)

3B20.Q301:
- Update SKX CPU H0 stepping microcode to MB750654_02006b06.
- Update CLX CPU B0 stepping microcode to MBF50656_04003102.
- Update CLX CPU B1 stepping microcode to MBF50657_05003102.
- Update Intel(R) SPS F/W to SPS_E5_04_01_04_505_0.
- Correct UPI corrected error threshold setup maximum to 32767.
- Make bad bar work only if boot in legacy mode.
- Implement power cycle after SCE import with /ni parameter in PowerCyclePolicy OEM module.
- [S5B] For rebranding case that still using Type3 Riser3, add riser type 1~3 of Riser 3 back.

3B19.Q103:
- [S5B/S5BQ/S5BV/S5BM/S5BT/S5BE] Implement latest USB2 PP1/PP2 EA settings.

3B19.Q102:
- Display option EPP profile.

3B19.Q101:
- Follow 5.14_PurleyCrb_0ACLA052 to update related modules  RC0610.D02 (2020.2 IPU PV)
- Update SKX CPU H0 stepping microcode to MB750654_02006a08.
- Update CLX CPU B0 stepping microcode to MBF50656_04003003.
- Update CLX CPU B1 stepping microcode to MBF50657_05003003.
- Update Intel(R) SPS F/W to SPS_E5_04_01_04_423_0.
- Update Intel(R) RSTe PreOS Components to v6.3.
- Update SMBIOS type 4 Max Speed for Cascadelake.
- Modify behavior of input invalid IP on IPv6 address to remain previous valid IP instead of replaced by :::::::.
- Add multiple NICs to the blacklist.
- [S5B] Add Virtual Slot ID VSLOT_RISER3_ID0 back and remove VSLOT_RISER3_ID1,2,3 for SMBIOS type 9 Riser 3.
- Follow Standard conclusion to let IPv4 related address back to previous valid address while input invalid address.

3B18.Q401:
- Follow 5.14_PurleyCrb_0ACLA051 to update related modules (RC0602.D02 IPU PV)
- Update SKX CPU H0 stepping microcode to MB750654_02006906.
- Update CLX CPU B0 stepping microcode to MBF50656_04002F01.
- Update CLX CPU B1 stepping microcode to MBF50657_05002F01.
- Implement Clearing Ppr Data Consumed bit in CMOS.
- Implement skip to check reserved IPv6 addresses.
- Improve the condition rule of getting MAC from Mellanox CX series card.
- [S5BQ] Add S5BQ new SKU "20x SAS/SATA + 4x U.2" support.
- [S5BT/S5BE] According new Board-ID to implement multi-default BIOS settings.
- [S5S/S5SP] Support new S5S/S5SP Cascade board IDs.
- [Redfish] Redfish MTU set it to 1400.

3B17.Q301:
- Follow 5.14_PurleyCrb_0ACLA050 to update related modules. (RC0602.D02 IPU PV)
- Update SKX CPU H0 stepping microcode to MB750654_02006901.
- Update CLX CPU B0 stepping microcode to MBF50656_04002F00.
- Update CLX CPU B1 stepping microcode to MBF50657_05002F00.
- Update Intel(R) SPS F/W to SPS_E5_04_01_04_381_0.
- Implement Send SHA512/SM3_256 PCR Bank Enable/Disable to BMC.
- Implement "Extended Type 17 Structure" as enable.
- Implement the case sensitive for HDD password.
- Modify "Hynix" to "SK Hynix" in SMBIOS and Redfish 
- Modify Setup: Grayout iSCSI and RAMDisk Configuration operation in user access level. 
- Modify Setup: Correct the help text string of PL1 Limit.
- Follow PCIe SPEC to check if Pcie Extended Next Capability Offset is invalid.
- [S5S/S5SP] Correct 'Correctable Error Threshold' default to 5000 per new QCT defintion. 
- [S5BT/S5BE] Modify SMBIOS type8.
- [Redfish] Set correct Scsi Device capacity.
- [Redfish] add DCPMM Namespace Size.
- [Redfish] Send MemoryType for DCPMM, NVDIMM-N/F, and DRAM to BMC when DIMM_INVENTORY_SMBIOS_V_3_2 is disabled.
- [Redfish] Not to send PcieInterface from Redfish.
- [Redfish] Show SAS with RAID card storage info when use redfish "/redfish/v1/Systems/Self/Storage/1/Volumes".
- [Redfish] Disable to send related information of SetupData.xml.
- [Redfish] Remove x-AMI that related with BMC LAN configuration.
- [Redfish] Add x-AMI of "MCTP Bus Owner" Option.
- [Redfish] Add x-AMI of "SNC" Option.
- [Redfish] Add x-AMI of "Perf P Limit" Option.
- [Redfish] Add x-AMI of "Link Speed Mode" Option.
- [Redfish] Add x-AMI of "Link Frequency Select" Option.

3B16.Q102:
- [S5BT] Update SMBIOS type8 for S5BT.

3B16.Q101:
- Follow 5.14_PurleyCrb_0ACLA049 to update related modules (RC0595.D04 IPU)
- Update SKX CPU H0 stepping microcode to MB750654_02000065.
- Update CLX CPU B0 stepping microcode to MBF50656_0400002C.
- Update CLX CPU B1 stepping microcode to MBF50657_0500002C.
- Update Intel(R) SPS F/W to SPS_E5_04_01_04_339_0.
- Update Intel(R) RSTe PreOS Components to v6.2.0.1034.
- Set memory correctable error threshold to 5000.
- Set memory leaky bucket timer period to 16.11 sec.
- Enable Send NVME SSD Information IPMI command to BMC
- Setup modify: Hide "Stale AtoS" and "LLC dead line alloc".
- Setup modify: Correct some Setup help string text.
- [RSD] Add delay time for some network card cannot send LLDP packet issue.
- [Redfish] Implement setting Pwr and Perf Profile to Custom when any related setting is set.
- [Redfish] Update x-AMI language for options in Setup.
- [Redfish] Send MemoryType for DCPMM to BMC.
- [S5B] Setup modify: Unhide memory 2933 related setup options.
- [S5BQ] Modify SMBIOS type 9 data.
- [S5BT/S5BE] Modify SMBIOS type 8.
- [S5BT/S5BE] Modify SMBIOS type 9.

3B15.Q401:
- Follow 5.14_PurleyCrb_0ACLA048 to update related modules (RC0591.D01 PLR2)
- Update SKX CPU H0 stepping microcode to MB750654_02000060.
- Update CLX CPU A0 stepping microcode to MB750655_03000012.
- Update CLX CPU B0 stepping microcode to MBF50656_04000029.
- Update CLX CPU B1 stepping microcode to MBF50656_04000029.
- Update Intel(R) SPS F/W to SPS_E5_04.01.04.323.0.
- Update RSD related module to 07.1.
- Define more detail memory type on OemIPMI command.
- Add DIMM DateCode into OEM IPMI CMD Set DIMM Information Param 7.
- Add DIMM Manufacturing Location into OEM IPMI CMD Set DIMM Information Param 7.
- [S5B/S5BQ] Add S5B/S5BQ GPGPU SKU support.
- [S5B/S5BQ] Implement S5B/S5BQ GPGPU SKU new PCIe hot-plug settings.
- Send RSD provision done to BMC even if no NIC been detected on system.
- Set onboard device slot number to 0 on SMBIOS type 190/192.
- Follow RSD SW request to modify RSD OEM type 210.
- Update to send correct Cascade Lake stepping L0/1(N0/1), R0/1(V0/1) info in ProcessorInfo sending to BMC.

3B14.Q301:
- Follow 5.14_PurleyCrb_0ACLA046_BETA to update related modules (RC0584.D01 PLR1)
- Update SKX CPU H0 stepping microcode to MB750654_0200005E.
- Update CLX CPU B0 stepping microcode to MBF50656_04000024.
- Update CLX CPU B1 stepping microcode to MBF50657_05000024.
- Update Intel(R) SPS F/W to SPS_E5_04_01_04_296_0.
- Improve the 1st boot time after BIOS upgrade with BIOS setting preserve condition.
- Implement Move BMC USB virtual CDROM disable command' from exitbootservice to POST end.
- [S5B] Implement customer-requested Setup settings
- [S5S] Implement customer-requested Setup settings
- [S5S] Implement S5SG/S5SF support/S5S series EA settings.
- [RSD] Modify the Socket Designation in SMBIOS Type 193.
- [Redfish] Modify "ChassisType" from "Sub Chassis" to "Sled" in BMC Redfish.
- [Redfish] Do not send DHCPv4 and DHCPv6 to BMC via Redfish.

3B13:
- Follow 5.14_PurleyCrb_0ACLA044 to update related modules (RC578.D07 MR3)
- Display "MMIO High Base" and "MMIO High Granularity Size" options for QCT project.
- Follow SI standard to unhidden options(Activate PBF, Configure PBF, RAPL Prioritization, SNC).
- Enable the case sensitive for HDD password.
- Update Redfish StringID for PCIe and network.
- Enable sending Processor ID information to meet QCT BMC OEM Standard Spec.
- Create [2T] option in "MMIO High Base".
- [S5BV] Follow new S5BV_RISER_ID_20190229_for_BIOS table to modify S5BV Riser 2/Riser 3 Configuration.
- [S5BV] Follow new S5BV_RISER_ID_20190227_for_BIOS table to add QSMC M1 test configuration.
- Update SMBIOS type 4 Max Speed for Cascadelake.
- Follow SI standard to add "IPv6 Configuration" under BMC network configuration.
- Follow SI standard to hide options(IPSEC Certificate, PXE boot wait time, PCI-E Port, Hot Plug Capable, Surprise Hot Plug Capable, PCI-E Port Link).

3B12:
- Follow 5.14_PurleyCrb_0ACLA043 to update modules (RC 576.D20 PV)
- Update ME to SPS_E5_04_01_04_256_0 from SPS_E5_04_01_04_251_0.
- Add Module RsdPurley_01 for RSD feature on Purley Platform.

3B11:
- Follow 5.14_PurleyCrb_0ACLA042 to update modules (RC 575.D01)
- Update Microcode to 0200005A for SKX H-0/M-0/U-0 stepping.
- Update Microcode to 0400001C for CLX B0 stepping.
- Update Microcode to 0500001C for CLX B1 stepping.
- Update SPS to SPS_E5_04_01_04_251_0 from SPS_E5_04_01_03_239_0.
- Add AEP dimm identify on RSD OEM type 197.
- Update OemPublishTables eModule to 06.1.
- Update Redfish Host/Basic/Advanced eModules to label 07 for Redfish 1.5 support.
- Show correct CPU stepping in Main page and "Processor BSP Revision" of setup page Processor Configuration when CLX L0 CPU is attached.
- Add new prefix string for some options in Redfish API.
- Implement Send Turbo mode status to BMC.

3B10:
- Follow 5.14_PurleyCrb_0ACLA039 to update modules (RC 566.D03)
- Update Microcode to 03000010 for CLX A0 stepping.
- Update Microcode to 04000014 for CLX B0 stepping.
- Update Microcode to 05000014 for CLX B1 stepping.
- Update SPS to SPS_E5_04_01_03_239_0 from SPS_E5_04_01_03_237_0.
- Sync boot device name in Redhat 7.3 and 7.4.
- Update RSD related module.

3B09:
- Follow 5.14_PurleyCrb_0ACLA037 to update modules (RC 561.D09)
- Update Microcode to 02000057 for SKX H0 stepping.
- Hide MCP root ports Setup options when CLX CPUs are attached.
- Update SPS to SPS_E5_04_01_03_237_0 from SPS_E5_04_01_02_224_0.

3B08:
- Modify Memory RAS Correctable Error Threshold help text value from Hexadecimal to Decimal.
- Implement RSD SMBIOS type198 for FPGA information.
- Follow 5.14_PurleyCrb_0ACLA036 to update modules (RC 559.D18)
- Update Microcode to 02000056 for SKX H0 stepping.
- Update Microcode to 04000010 for CLX B0 stepping.
- Update for remove the duplicated CentOS and Redhat in Boot Options and Boot override.
- [S5B/S5BQ] Modify SMBIOS type 8 and 9.

3B07:
- Follow 5.14_PurleyCrb_0ACLA034 to update modules (RC 0556.D04)
- Update Microcode to 02000055 for SKX H0 stepping.
- Update Microcode to 0300000F for CLX A0 stepping.
- Add Microcode 0400000A for CLX B0 stepping.
- Update ME to SPS_E5_04.01.02.224.0 from SPS_E5_04.01.02.200.0.
- Issue a power cycle when Core Disable Bitmap(Hex) is set to enabled from disabled.
- Enable ECRC on end device depended on the ECRC setup option of the corresponding root port to Purley_refresh.
- Update for ignoring IO resource padding.
- Improve the subgroups bbs priorities cannot be preserved during BIOS update.
- Add error events to QCT Event Data 1 for DCPMM error log and only try to report when DDRT alert is enabled for the transaction cross error type.
- Follow the latest DCPMM population rule to update SMBIOS type 16 maximum capacity for memory 1-1-1 configuration.
- Modify Setup "Extended Tag" default value token according to 5.14_PurleyCrb_0ACLA032.
- Modify Setup strings "IPV4"/"IPV6" to "IPv4"/"IPv6".
- Modify SMBIOS type 16 of 2-1-1 configuration to meet DCPMM Snapshot requirements.
- Update for BMC SEL no log any event when triggering DMI correctable error via ITP.

3B06:
- Follow 5.14_PurleyCrb_0ACLA031.1_BETA to update modules (RC 0549.D13)
- Update Microcode to 02000050 for SKX H0 stepping.
- Mask Unexpected Completion uncorrectable error to Purley_refresh.
- Update ME to SPS_E5_04.01.02.200.0 from SPS_E5_04_01_02_161_0.
- Unhide "Security Device Support" according to SI standard.
- Avoid reporting 2LM mismatch warning log if user do not request 2LM mode indeed.
- Follow SI standard to hide "RAM Disk Configuration" and "AppDirect cache".
- Enable USB Rndis Driver on S5B and S7D

3B05:
- Do not display status message on the screen for Redfish Inventory posting.

3B04:
- Follow 5.14_PurleyCrb_0ACLA030_BETA to update modules. (RC0546.D06)
- Improve send MAC address to BMC for Mellanox ConnectX-4 to ConnectX-6 series card.
- Improve PCH PCIe error log.
- [Redfish] Update Redfish related eModules.
- [Redfish] Implement send storage info to BMC via Redfish Host Interface.

3B03:
- Update AST2500 eModule.
- Update ME to SPS_E5_04_01_02_161_0 from SPS_E5_04_01_00_119_0.
- Update Microcode to 0300000D for CLX A0 stepping.
- Follow 5.14_PurleyCrb_0ACLA028_BETA to update modules. (RC0543.D03)
- Implement use Redfish Host Interface to support BIOS update via Redfish.
- Implement PPR event log in QCT projects.  
- [S5BT] Correct S5BT SMBIOS Type 9 information.
- [S5BT] Support hot-plug function on NVME devices.
- [S5BT] Follow EA suggestion to modify configurations
- [S5BT] Remove Uplink Precursor/Cursor/Postcursor override to use default settings.
- [S5BT] Add S5BT to support DetectRetimerCard feature.
- [S5BT] Correct PCH UpLink vga/tsm settings
- [S5BT] Support MAX payload size to 512 bytes for S5BT on specific SKU(0x0).

3B02:
- Update Microcode to 0200004D for SKX H0 stepping.
- Update SPS to SPS_E5_04.01.00.119.0
- Update AST2500 VGA OpROM to v1.08.00
- Follow 5.14_PurleyCrb_0ACLA026_BETA to update modules. (RC537.D06)
- Implement PCIe leaky bucket Timer more precisely
- Implement other IIO error SEL in last boot.
- Implement BMC LAN IPv6 Static Router1 Prefix Length input in setup menu. 
- Implement send SMBIOS table before TSE.
- Setup modify: Recover the BIOS settings which modified for Apache Pass DIMM.
- Setup modify: Adjust setup "USB Configuration".
- Setup modify: Hide "Suppress PTT Commands" option
- [Redfish] Add SMBIOS Type 42 to report Redfish Host Interface.
- [Redfish] Modify help strings in Redfish BIOS Attribute Registry.
- [Redfish] Implement adding additional BIOS option in Redfish dynamically.
- [Redfish] Change to use Redfish Host Interface to send BIOS config data to BMC.

3B01:
- Initial official released version.

===========================================================================================
                             FEATURES REMOVED
===========================================================================================
3B27.Q401:
- N/A.

3B26.Q301:
- N/A.

3B25.Q201:
- N/A.

3B24.Q101:
- N/A.

3B23.Q301:
- Remove the fix of system will reboot multiple times when CPU0/CPU1 "Core Disable Bitmap(Hex)" are set to different values.

3B22.Q201:
- N/A.

3B21.Q402:
- N/A.

3B21.Q401:
- N/A.

3B20.Q301:
- N/A.

3B19.Q103:
- N/A.

3B19.Q102:
- N/A.

3B19.Q101:
- Disable PCH PCIe root port 6 (1-based).

3B18.Q401:
- N/A.

3B17.Q301:
- Disable to send detail memory type to BMC.

3B16.Q102:
- N/A.

3B16.Q101:
- [RSD] Remove PCH Root Ports from type 192/165,
- [Redfish] Remove the CRB Asset Tag information of Inventory Storage Device.
- [Redfish] Remove FPK Port # Present from Redfish BIOS setting.

3B15.Q401:
- N/A.

3B14.Q301:
- N/A.

3B13:
- [S5BM] Remove Setup EVT default settings.

3B12:
- N/A.

3B11:
- N/A.

3B10:
- N/A.

3B09:
- N/A.

3B08:
- N/A.

3B07:
- Remove overrides of keeping old label codes because build errors do not exist anymore.
- Remove "Administrator Password" and "User Password" from Redfish BIOS OOB Config.

3B06:
- Remove Redfish Host Interface Network device from UEFI iSCSI setting.

3B05:
- Remove extra SMBIOS type 42
- Remove OEM SMBIOS Type 133 created by Intel RC.

3B04:
- N/A.

3B03:
- N/A.

3B02:
- N/A.

3B01:
- N/A.

===========================================================================================
                             ISSUES FIXED
===========================================================================================
3B27.Q401:
- N/A.

3B26.Q301:
- N/A.

3B25.Q201:
- Fix SATA device string below FIXED BOOT ORDER Priorities is mismatch in Legacy mode issue

3B24.Q101:
- Fix #404871 Run "Hardware Security Testability Interface Test" failed.
- Fix #398283 SMASH show duplicate MAC address of E810XXVDA2G1P5 NIC card after switch BIOS to Legacy mode.(MCS ID:4519.1)
- Fix #328227 The description and Severity of ''Correctable Memory Error Logging Disabled'' and ''Correctable ECC Error Logging Limit Reached'' events are not meet event log table v4.58 definition.
- Fix SMI Vulnerabilities issue, follow EIP#696018 to add fix patch on 
  AmiModulePkg-(GenericSio/LegacySerialRedirection/TcgStorageSecurity/HddSecurity) module.

3B23.Q301:
- Fix #387294 WebUI display duplicate MAC address of Mellanox MCX631102AC-ADAT(MCS ID:4555.1) NIC card.
- Fix #387646 BIOS 3B22.Q201 SMBIOS type17 info "Type Detail" is wrong.
- Fix the "Administrator Password" help text incorrect with the full Samsung PM983 drives.
- Fix that Debian 10 boot fail when secure boot is enable.

3B22.Q201:
- Fix #384565 that there are 2 Debian OS options shown in Boot Override after install Debian 10.11.
- [S5SP] Fix #224846 Use two PCIe SSD build RAID1 via VROC , the HDD slot 4 will be trigger fail/rebuild LED when hotplug HDD slot 5, but the HDD slot 5 won't trigger fail/rebuild LED.
- Fix PPR event is not correct when bad DIMM is used in CPU1.
- Fix that PPR events will be recorded even if PPR is not executed.
- Fix system cannot boot into USB via Redfish/IPMI persistent command in first boot when MB is mounted CD/DVD.
- Fix system cannot record other non-ECC memory errors when Correctable ECC Error logging is disabled.

3B21.Q402:
- Fix #377997 When boot to PXE via IPMI and Boot Option#1 not set to network, it will jump over to next Boot Option, if first port cannot boot into PXE
- [S5SG] Fix #373184 BIOS BBS Priorities didn't display ''slot X'' in every boot option.
- Fix security issues by enabling flash descriptor region Lock.

3B21.Q401:
- Fix #365304 After flash 3B20.Q301 with preserve by WEBUI, BIOS ''Boot override'' show UEFI: PXE/HTTP IPv4.../PXE/HTTP IPv6 information(Legacy Mode).
- Fix #366120 BMC sensor "Temp_CPUx" no reading after update BIOS 3B20.Q301
- Fix #366805 The F11 function key messages dispalyed 'Press <F11> to enter boot option', but it should be 'Press <F11> for BBS POPUP menu'
- Fix #367011 The BIOS item "PTT Support" was gray out and also cannot change the setting.
- Fix Dimm D0 E0 F0 PPR not occur after Dimm A0 B0 C0 PPR occurs issue.

3B20.Q301:
- Fix #341596 BIOS item "Dirty warm reset" can't switch to enable.
- Fix #345572 SMBIOS Type9 Riser3 M.2 Slot is not match with Riser3 silkscreen.
- Fix 3 abnormal "44975" string on setup menu issue. Fix iSCSI driver option cannot grayout by .vfr issue.
- Fix CVE-2019-14560 base on the modification provided by AMI.
- Fix E810 don't list under Boot Override when the system is the legacy mode.
- Fix UCE PPR SEL can't be executed successfully in some conditions.
- [S5T] Fix the SMBIOS Type 9 of S5T OCP slot not match silkscreen.

3B19.Q103:
- N/A.

3B19.Q102:
- Fix #344128 After install RHEL8.3 with QS-3516B-R6-PD32_4G(FW 5.140.00-3319),system log has error log ''FuPluginUefi failed to add /sys/firmware/efi/esrt/entries/entry0: ESRT GUID'',
- Fix #345143 After install AEP DCPMM ,no "Intel Optane DC Persistent Memory" option in BIOS Advance page
- Fix #345192 PCIe SLOT number in SMBIOS/BIOS Boot override doesn't match silkscreen
- Fix #345572 SMBIOS Type9 Riser3 M.2 Slot is not match with Riser3 silkscreen.

3B19.Q101:
- Fix #283156 Slot Designation string of SMBIOS Type 9 doesn't match HW silkscreen
- Fix #329619 When enable ''Disable Block Sid'', the password is invalid when keying correct NVME SSD Password
- Fix CurrIpmiOverLan won't be updated when GetPortFirewall status is failed.
- Fix BIOS fail to send firmware version to BMC by IPMI command.

3B18.Q401:
- Fix #321628 BMC SEL record "Bus Correctable Error" during the BIOS FW flash.
- Fix #321996 When inject UCE via APEI and trigger memory disable function, it will have system hang after reset.
- Fix #322723 Stream result "Triad" value can't reach 98% of previous BIOS version Stream Triad at least.
- Fix #322138 Micron 64G dimm performance can't reach expect pass value with BIOS hyper threading disable.
- Fix #324344 "Multi Rank Sparing" is not present in AMISCE dump file when dump with prameters /lang.
- Fix #321964 Can't format pmem0 when "Interleave NVDIMMs" is enabled.
- Fix Memory Topology shows incorrect Dimm size when "Memory Rank Sparing" is enabled.
- Fix system will reboot multiple times when CPU0/CPU1 "Core Disable Bitmap(Hex)" are set to different values.
- [Redfish] Fix MacAddress format of device w/o SNP support does not match Redfish schema.
- [Redfish] Fix some options need to communicate BMC can not be set via Redfish and SCE.
- [Redfish] Fix "BMC Console Redirection Enable", "BMC SOL Bits per second", and "BMC LAN Port Configuration" can not be modified by Redfish and SCE.
- [Redfish] Fix "BMC Console Redirection Enable" in BIOS Setup is grayout and user can't modify it, but still can use Redfish to set it.

3B17.Q301:
- Fix #302747 SCE tool can modify BIOS setting without password when BIOS is set administrator password.
- Fix #304364 The system MAC cannot display under dashboard of WEBUI.
- Fix #304558 The system MAC(UEFI/Legacy) cannot display via SMASH.
- Fix #302780 There are some items can be changed via SCE without password when administrator password in BIOS setup is setting.
- Fix #300111 The all items in the Network Stack Configuration will not load default after flash BIOS with /N /CLRCFG.
- Fix #301253 "Boot mode" and "Boot Order Priorities" in BIOS setup did not load default after system reboot.
- Fix #308809 SHA384 PCR Bank will not preserve.
- Fix #308921 The content of status message has wrong after create Multiple Namespaces in the existing Pools via redfish.
- Fix #307614 Redfish response lost "PCIe LAN card" when get URI under /redfish/v1/Systems/Self/EthernetInterfaces.
- Fix #308926 /redfish/v1/Systems/Self/Storage/${Storage_i nstance}/Drives/${Drive_instance}, "HotspareType", "IndicatorLED" attribute shows strange value.
- Fix #309189 /redfish/v1/System/Self, HealthRollup in Status of MemorySummary always show Critical
- Fix #309188 /redfish/v1/System/Self, HealthRollup in Status of ProcessorSummary always show Critical
- Fix #309736 There are two format in ACPI Table "OEM Table ID".
- Fix #312011 The Height and Number Of Power Cords values error via dmidecode -t 3 dump.
- Fix #295484 "Altitude" will not be preserved.
- Fix #312088 The SMBIOS usb0 SubnetMask IP is different with Redfish and ssh debugger.
- Fix #313155 Some PCIE uncorrectable error's error ID is incorrect in WEBUI SEL.
- Fix #314280 BCOM P2100G NIC MAC address shows 0 on BMC Web-UI in legacy mode.
- Fix #318037 OS recorded abnormal events"Failed to add BAR[x]" and "Unable to free BAR[x]".
- Fix #317160 BIOS "CPU P State Control" page cannot see [Config TDP] and [Intel Speed Select] options.
- Fix #309528 BIOS options "Secure Boot" and "Secure Boot Mode" should not be changed to default after update BIOS.
- Fix #299697 Slot Designation string of SMBIOS Type 9 doesn't match HW silkscreen.
- Fix #315842 IPv6 Dynamic Prefix Length is always 0.
- Fix #298753 "Security Device Support" setting should be kept, after executing BIOS Restore Defaults, then Save Changes and Reset.
- Fix correct boot device when enter command "ipmitool chassis bootdev cdrom". 
- Fix Correct the severity to Non-Fatal Error for hot removal case.
- Fix NVDIMM not updated correctly in SMBIOS type 17.
- Fix system cannot enter AMI Virtual CDROM after BMC mount two or more same image.	
- Fix that system need to sign the driver again in Linux OS when "Secure Boot"=Enabled during BIOS update in the second time.
- Fix TPM Vendor ID name in SMBIOS Type 43.
- Fix that ProductInfo fields in setup FRU is inconsistent to others while FRU fields are empty.
- Fix Secure Boot disabled at 2nd system reset after set next boot to Legacy via IPMI or Redfish
- Fix ipmi boot with persistent mode function fail when set the BIOS admin password. 
- [Redfish] Fix MacAddress format does not match Redfish schema.
- [Redfish] Fix system won't boot into build-in shell when set BootSourceOverrideTarget as UefiShell.

3B16.Q102:
- Fix #302747 SCE tool can modify BIOS setting without password when BIOS is set administrator password.
- Fix #301253 Loading default by F9 then save and exit, the "Boot mode" and "Boot Order Priorities" in BIOS setup did not load default after system reboot.
- Fix #306720 DIMM Type "No DIMM Present" is displayed on Web UI's System Inventory, actually DDR4 was plugged in system.
- Fix #309692 There are two format in ACPI Table "OEM Table ID".
- Fix #312011 Height and Number Of Power Cords in SMBIOS type 3 are incorrect.
- Fix #299697 Slot Designation string of SMBIOS Type 9 doesn't match HW silkscreen (SKU:All Flash)
- Fix "err_log_entries" number will increase under Linux when install Samsung PCIE M.2 and TPM 2.0.
- Fix BMC will return time-out(completion code:0xC3) when send OEMVAR_BOOT to BMC.
- Fix that system need to sign the driver again in Linux OS when "Secure Boot" is Enabled during BIOS update in the second time.
- [S5S/S5SP] Correct 'Correctable Error Threshold' default to 5000 per new QCT defintion.

3B16.Q101:
- Fix #284623 When sysyem install PCIe SSD, legacy device should not show on Boot Override.
- Fix #295062 BMC record Correctable ECC error log after inject few times ECC error via ITP.
- Fix #276784 The GPU "Unidirectional P2P=Enabled Bandwidth Matrix" test.
- Fix #275360 BIOS setup menu will show "PCI OUT OF RESOURCES CONDITION" message when install three of the Tesla M10 GPU card.
- Fix #283324 System was often hung with black screen after POST during AC cycle test.
- Fix #295039 System hang with black screen during AC cycle.
- Fix #281581 The window show "Save & reset".
- Fix #296026 Riser 3 B0 slot port will change via ITP.
- Fix #298027 The "Contained Element Record Length" value should be set to 0.
- Fix #297627 BMC record 0xA109:(FP FRU - PD Custom Field 1 not implement).
- Fix #299583 SMBIOS Type3 "Number Of Power Cords" display incorrect value.
- [RSD] Fix Slot ID of type 192 for devices under PCH Root Port.
- [Redfish] Fix FirmwareRevision/FirmwareApiVersion sent incorrect to BMC via Redfish

3B15.Q401:
- Fix #285739 [S5BT] There are some data of SMBIOS Type8,Type9 not match HW SPEC silkscreen.
- Fix #269377 User shouldn't change iSCSI Configuration and Driver Health on BIOS Setup with user privilege.
- Fix #276784 [S5BV]The GPU "Unidirectional P2P=Enabled Bandwidth Matrix" test result of T4 on S5BV is FAIL.
- Fix #281581 The window show "Save & reset" but the function info show "Save & Reset" when type the keyboard "F10" button.
- Fix #276267 GET /redfish/v1/Chassis/Self/NetworkAdapters/{NetwrokAdapter_instance}/NetworkPorts/{NetworkPort_instance} response incorrect data when unplug LAN cable and reboot OS. (LinkStatus/SignalDetected)
- Fix #288288 HDD Data information is incorrect in QSM 1.8.3.5.
- Fix #285619 [S5BQ]The riser 3 slot 1/2 information should be x8/x16 not x16/x8 via smbios(D0 A3BF1/D0 A3BF2)
- Fix #285236 Administrator Password didn't preserve successful after use YAFUFlash2 Update BIOS with Preserve
- Fix #283875 BIOS password not preserved after update BIOS via afutool or WebUI (w/ NVRAM preserve)
- Fix #283136 [S5B] Slot Designation string of SMBIOS Type 9 doesn't match HW silkscreen.
- Fix #479494 With CLX N SKU CPU, the value of High/Low Priority Core Count and Base Frequency in SMBIOS Type 210 is incorrect.
- Fix #281233 SMBIOS type 210 information not match SMBIOS SPEC definition.
- Fix #273915 The PCIe SlotNo of Extended PCIe Error event doesn't match BIOS Boot Override display.
- Fix #283209 Redfish record wrong HDD FW version in "/redfish/v1/Systems/Self/Storage/1". (P4610 3.2T)
- Fix #281173 Lack "(DDR4)" string in "usable memory" of Main page.
- Fix #282392 Redfish response have one incorrect attribute about "Revision".
- Fix #251805 P1100p NIC Card MAC address is "00:00:00:00:00:00" under BMC 4.22/4.50 with LEGACY mode.
- Fix #278786 The status of FPK Port # Present is changed from enabled to disabled after updating BIOS with preserve NVRAM setting.
- Fix SecureBootSetup variable not preserved when flash BIOS with /CLRCFG.
- Fix NVRAM_PERSISTENT_VARIABLES_LIST not preserved when flash BIOS with /CLRCFG.
- Fix fill wrong slot id to SMBIOS type 192.
- Fix BIOS may not do Redfish communication with BMC permanently until next BIOS upgrade action.
- Fixed system will hang when use specific CPU that not support Speed select and TDP level.
- Fixed RSD provision fail when set parameter UpdateMdr to ture.
- Fixed BIOS not send LLDP packet when system do RSD provision.

3B14.Q301:
- Fix #242007 Memory Rank information is not match between MCS and SMBIOS table.
- Fix #271782 When set "security boot" to enable and "Factory Key Provision" to Enabled, "EFI Shell" will disappear in boot override.
- Fix #271383 When set "Enable Intel TXT" to disable , dump SMBIOS via command "dmidecode -t 196" will keep on "01" instead of "00".
- Fix #265448 The SMBIOS Type 9 record M.2 Slot , but "PCIe Riser Interface" did not have M.2 slot on HW SPEC.
- Fix BMC WedUI don't show any MAC address when send the seventeenth MAC to BMC.
- Fix 128GB and 256GB AEP will show rank 4 in SMBIOS type 17.
- Fix AEP rank in memory topology is not match with SMBIOS type 17.
- [Redfish] Fix the incorrect value of StatusIndicator of NVMe device.
- [Redfish] Fix VirtualNic of inventory information is not exist if no any LAN card in the system.

3B13:
- Fix #270928 BMC SEL record POST Error "0xA33F : DIMM configuration problem. (CPU0)" twice under MM with the invalid setting.
- Fix #270337 There is an item "Launch EFI shell from filesystem device" of BIOS bootoverride which is not defined in BIOS Std SPEC v3.10 and QCT Purley BIOS SPEC v1.6.
- Fix #272715 BMC SEL record POST Error "0xA33F : DIMM Configuration Problem.(CPU0)" with 16G 2666MHz DIMM (8 RDIMMs+4AEPs,Memory mode)
- Fix CPU stepping in Main page is incorrect when CLX L1 CPU is attached.
- Fix #272285 System MAC information for OCP card should be "OCP" instead of "PCIe" in device info page of BMC WebUI.
- [S5BM] Fix S5BM FP FRU SKU ID 00 will always report POST error "(0xA109) FP FRU - PD Custom Field 1 not implement"
- [S5BM] Fix SMBIOS type 9 data do not exist.
- Fix Intel Speed Select cannot config via BIOS setup menu.
- [S5BQ] Fix #257304 The SlotNumber on SMBIOS is mismatch with BIOS boot override.
- Fix #269483 When move cursor to CPU_1, no CPU information appears under System Inventory page. CPU 1 information will be null in the WebUI.
- Correct OEM Type 210 Intel Speed Select configuration count and TDP value.
- Fix to send correct Cascade Lake stepping B0/B1 info in ProcessorInfo sending to BMC.

3B12:
- Fix #242007 Memory Rank information is not match between MCS and SMBIOS table.(AEP DIMM)
- Fix #271023 The stepping of CPU CLX R0 is not matched between BIOS and DCL SPEC.
- Fix #239705 There is no MAC address information for MCX555A-ECAT in BMC WebUI and SMASH if boot mode is "Legacy".
- Fix #221532 Can't boot into windows 2016 after install Windows 2016 in Samsung HGST 3.2T.

3B11:
- Fix the wrong setting on Uncorrectable Error Detect Status Mask(0x218).
- Fix #260461 The system can not boot into OS W2019 after set DCPMM to App direct mode.(Memory mode and RDIMM pass)
- Fix #265639 "Unconfigured capacity" always show 0 B when Set Reserved[%] to X (X>0) in BIOS Setup UI.
- Fix #264103 POST Error report the incorrect DIMM location with invalid settings or configuration.
- Fix #262927 BIOS menu will keep blank option under DCPMM page which should skip this row when press up/down key.
- Fix #264644 & #259518 There is no definition of VLAN related options in BIOS spec and not match with SI Std. 

3B10:
- Fix that there are 2 Fedora OS options shown in Boot Override after install Fedora 27.
- Fix BSSA RMT(Rank Margin Test) does not run.
- Fix #260456 The location of item "Config 2" for "Intel Speed Select" in BIOS Setup UI should be consistent with ISS other items("Base" and "Config 1")
- Fix #266065 When system use the 6240C CPU, the BIOS did not show out the Intel Speed Select option.
- Fix #259418 SUT stop at 0xA2 and not appear the screen for key in recovery key after Bitlocker set then reboot SUT without the recovery key.
- Fix #249882 The system pop-up abnormal word after press "Del" key during BIOS post.
- Fix #263633 SUT cannot boot into PXE with HTTP IPv4 through I357-T2.
- Fix #261406 BMC did not log "Uncorrectable Error" but logged one undefined Memory event when injecting memory Multi-Bit error
- Fix #262786 After clear CMOS by jumper, the BMC SEL Record the "0xA104:CMOS/NVRAM configuration cleared" four times.
- Fix #257343 The USB LAN devices configuration should be hidden under BIOS advanced page in UEFI mode or Legacy mode.
- Fix #261879 The total memory info shown "unknown" under POST.

3B09:
- Fix #257914 - SEL did not have a PCIe error after injecting PCIe error for 11 times by ITP (Threshold=10 by default).
- Fix #257776 - SEL did not have 'Uncorrectable ECC error' after injecting memory uncorrectable error by ITP.

3B08:
- Fix SEL will show "undefined Memory event" when inject memory uncorrectable error to DDR4.
- [S5BT] Fix slot ID are different between SMBIOS type 190 and SMBIOS type 9.
- Fix #245833 - OpROM of QS-8204-8i on UEFI mode "Driver Health Quanta SmartROC QS-8204-8i" item should not be shown in "Advanced" label.
- Fix #257455 - BMC SEL logs will record garbled words on WebUI page after flash BIOS FW version to 3B07.
- Fix #257763 - Sometimes, no SEL log after inject PCIe correctable error if threshold > 1.(passed if threshold=1)
- Fix #255455 - Phy board X527-DA2 would show 2 device and the one has icorrect sub vendor ID, sub device ID, device type, Rate Width, and Rated Speed information.
- Fix PCIe Fatal/Non-Fatal error happens on the Root Port cannot be logged if the Root Port's PCI Device number is not zero.
- Fix #258236 - After setting jumper to clear CMOS, there is no "0xA104:CMOS/NVRAM configuration cleared" message at POST screen, but clear CMOS successfully. (BMC recorded clear CMOS event)
- Fix #256695 - IPv4 configuration information will show "000.000.000.000" or "00-00-00-00-00-00" after changing "Configuration Address source" to "Static or Dynamic on next reset". But WebUI can login and show correct IP address.
- Fix #255977 - SUT will auto reboot and record memory error after inject PCIE non-fatal error then one more PCIE correctable error via APEI.

3B07:
- Fix system can't power on when only with one dimm(A0) and one AEP(A1).
- Fix SMBIOS BCD Revision display incorrectly.
- Fix that not all ports can enable ECRC depended on the ECRC setup option successfully.
- Fix that SUT didn't boot in first order "HDD" when Restore factory default via WebUI.
- Fix MAC address does not show on WebUI when disable "IPv4 PXE Support"
- Fix onboard LAN OPROM policy is not workable.
- Fix system cannot boot into UEFI OS after updating to 5.14_PurleyCrb_0ACLA032
- Fix BIOS boot order cannot be modify via IPMI "Set System Boot Options Command" without device of the group list in "Boot Override".
- Fix can't boot into the later order of NVMe SSD each with Legacy OS install.
- Fixed Type 197 Memory Device Handle not match to Type 17 in MemSlotConfig_112 configuration.
- Fix BMC SEL no log any event when triggering DMI correctable error via ITP.
- Fix "Network Stack Configuration" page does not show in SCE dump and some setup settings can't be modified.
- Fix the "Network Stack Configuration" setup page is not match with SI standard SPEC.
- Fix invalid value of parameter "Bytes to read" to IPMI Command "Get SDR" (Record Type 11h)

3B06:
- Fix #249884 - [DVT] [BIOS 2B04] SUT boot time is long during POST about 7 mins after reset.
- Fix #248206 SMBIOS only displayed 14 DIMM slot information in type 197 but the system installed 16 pieces DIMM.
- Fix #247425 - [DVT][BMC 2.02.00] SUT boot mode will not change to Legacy mode via IPMI command.
- Fix #244787 - [EVT] It spent over 5 minutes to load the image when SUT boot to RHEL7.4 image by LOM i210 / OCP MCX4421A-ACAN / PCIe MCX4121A-ACAT PXE IPv4.
- Fix #250710 - [DVT][BIOS 2B05] BIOS initialization stop working at AC cycling loop 17 as attached image.

3B05:
- Fixed #248810 POST error of BMC jumper disable shows "0xA106 BMC Failed (Self Test Fail)" which is incorrect, it should be "0xA105 BMC Failed (No Response)".
- Fixed #248663 - [DVT] HTTP IPv6 couldn't boot successfully by LOM i210 or Mellanox MCX4421A-ACAN OCP mezz card.
- Fixed #243698 - [EVT] Change boot device settings via IPMI, but the settings does not work in next boot. (HDD /CD-ROM failed)
- Fix boot too slow on postcode B4

3B04:
- Fixed #244074 BMC IPv6 IP address is empty in BIOS Setup menu.
- Fixed #246711 BIOS settings cannot be preserved if update BIOS via Yafuflash(preserve script) and WebUI(select preserve option). 
- Fixed #246836 Suggest to set Mirror Mode to grey out when Memory Rank Sparing mode is enabled. 
- Fixed dummy option would show up after loading default.
- Fixed changed the ISS item to "Config 1" or "Config 2", system would always trigger reset in MRC.

3B03:
- Fixed duplicate MAC addresses on WebUI under Legacy mode with Qlogic LAN card.
- Fixed the format of usable memory in Main Page.
- Fixed USB device will not change to first boot device in legacy mode after issuing IPMI next boot.
- Fixed duplicated CentOS in Boot Options and Boot override.
- Fixed #241909 Some options still can be set when the Access level is User
- Fixed #241970 Some items/options/settings are not match with BIOS Spec V0.12.
- Fixed #243308 System will waiting for more than 2 minutes on BIOS POST screen after system reboot.
- Fixed #242015 USB flash drive will disappear under EFI SHELL after keyin command "map -r".
- Fixed #243124 The security of the SATA HDD still be "frozen" after disable the secure erase first and then enable under BIOS setup.
- Fixed #242833 SUT cannot boot to RHEL7.4 with 2U-2Slot Riser and 4NVMe.
- Fixed #244211 No TPM info in SMBIOS Type43.
- Fixed #245234 System mode under Secure Boot still can be switched to User/Setup mode when the Access level is User

3B02:
- Fixed MAC address don't show in WebUI with SolarFlare LAN card under Legacy mode
- Fixed No System MAC on WebUI under Legacy mode with Qlogic LAN card
- Fixed the system may hang when boot into DOS.
- Fixed the system may hang in POST if many PCIe cards are installed.
- Fixed RSD OEM SMBIOS's sSATA device model String will be cut. 
- Fixed use PCIe slot number instead of NVMe namespace for Port Designation of OEM Type 194.  
- Fixed the duplicated question with Config TDP setup option. 
- [Redfish] Fixed that Redfish BIOS Current Setting "AttributeRegistry" value sometimes is incorrect.
- [Redfish] Fixed BIOS option "Legacy OpRom Support" cannot be configured via Redfish in some specific configuration.
- [Redfish] Fixed some BIOS options' default value in Redfish BIOS Attribute Registry are incorrect.
- [Redfish] Fixed that "ChassisType" = "Other" in BMC Redfish but SMBIOS Type 3 info is actually SubChassis.
- Fixed #241522 wrong total memory size under main page when install AEP.
- Fixed #219640 The error ID is "FF" of Extended PCIe Error event when trigger Malformed TLP error via Agilent card.
- Fixed #219653 The error ID is "FF" of Extended PCIe Error event when trigger "Surprise Link Down" via Agilent card.
- Fixed #241879 SEL logged "System Firmwares POST Error | Unspecified | Asserted" 3 times after reset SUT.
- Fixed #241432 After change BIOS to legacy mode the system can not boot into BIOS. 
- Fixed #241346 Can't boot OS via Redfish modify BIOS settings.
- Fixed #241522 wrong total memory size under main page when install AEP.
- Fixed #239399 BIOS cannot setup IPv6 Router IP Address and the Router IP Address is empty if modified in BMC WebUI. 
- Fixed #242855 System will stop in BIOS POST(C1) after set force boot from PXE directly via IPMI.
- Fixed #241338 The CPU max speed in SMBIOS table type 4 shows 4000MHz, but the max speed is 3.6GHz on Intel SKL-SP snapshot.
- [S5T] Set unused HSIO 14-17 default to sSATA port from based on native GPIO to workaround sSATA controller sleep to D3 while entering OS on specific MB.

3B01:
- N/A.

[END OF RELEASE NOTES]
